Adam Taylor MicroZed Chronicles: Interrupt Latency

Continuing with Adam Taylor's tutorials in his MicroZed Chronicles on the XADC. This post relates to issue 105, which can be found using the link at the bottom of the page.

What I learned from Adam's Tutorial:

Interrupt Latency: The time between the interrupt being raised and the interrupt being serviced.

Once a signal is in the XADC and the Zynq SoC, it is necessary to ensure that the application has been designed properly to meet the requirements and perform in the way intended.

Interrupt latency plays a major role in performance. 

Some issues that can impact interrupt latency are:
  1. The presence of an operating system
  2. The complexity of the ISR (Interrupt Service Routine)
If interrupt latency is not considered, the application could fail depending upon the latency period, latency consistency and the time taken for the ISR.

If latency is too great or ISR execution is too long, events can be missed. When this happens, it results in an unreliable system with sporadic failures. 

To determine interrupt latency it is necessary to know when an interrupt is asserted and when the ISR starts. To find this information, the AXI Timer can be used.

The AXI Timer provides the ability to load an initial value and count up until a terminal value is reached. This will require the following AXI Timer Features: 
  1. The ability to auto reload -- the interrupt counter reloads and continues counting.
  2. A freeze input that stops the AXI Timer from counting when asserted. The ISR can assert this signal to stop the counter.

These provide the ability to accurately determine how long it takes to service an interrupt and then calculate the interrupt latency. 




VIVADO:

Add the Processing System
Add 2 AXI Timers
Add 2 Slices

For both of the Slices, double click and change their Din Width to 2.

Double click on the Processing System:
Under MIO Configurations
  1. GPIO > Check EMIO GPIO > Change width to 2
  2. Check USB0
  3. Check UART1
Under Interrupts: Check Fabric Interrupts > Expand PL - PS Interrupt Ports > Check Core0_nFIQ and Check Core0_nIRQ > OK

Do not Run the Block Automation only run the Connection Automation

Additional Connections to be made:
  • Connect Core0_nFIQ to the axi_timer _1 interrupt
  • Connect Core0_nIRQ to the axi_timer_0 interrupt
  • Right click on DDR and make external
  • Right Click on Fixed_IO and make external
  • Connect (PS) GPIO_0 [1:0] to both xlslice Din
  • Connect Dout of slice_0 to freeze on axi_timer_0
  • Connect Dout of slice_1 to freeze on axi_timer_1
 Save > Validate > Create HDL Wrapper > Generate Bitstream

When Finished this is what your Block Design Should Look Like:





****Check next blog for part 2 
  http://zedboard.org/content/microzed-chronicles

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