Adam Taylor Microzed Chronicles: XADC with Real World Signals

Continuing with Adam Taylor's tutorials in his MicroZed Chronicles on the XADC. This post relates to issue 104, which can be found using the link at the bottom of the page.

What I learned from Adam's Tutorial:
  • An XADC is used to read in an analog signal and process the information.
  • To interface with the XADC an AXI interface is needed
    • Interface Options Include: 
      • Connecting with an AXI4-Lite Interface
      • Adding an AXI streaming interface to add further signal processing (like the FIR Filter)
  • The first choice that needs to be made is the selection of the input pins
    • The XADC has two dedicated differential input pins, Vp and Vn, which can be used to sample analog signals.
    • There are also 16 auxiliary inputs that can be used.
      • These have a lower FRBW (Full Resolution Bandwidth) of 250 kHz whereas the dedicated inputs have an FRBW of 500 kHz .
    • If using signals near the max Nyquist frequency, use the dedicated  inputs. 
  • If there are more than one signal or channel, the external multiplexer can be used.
    • Note that if the external multiplexer is used, it will reduce sample rate of the input signals.  
  • The XADC can sample a channel up to 1Msamples/sec. 
  • The DRP Clock determines the actual sampling rate and it is connected directly to the AXI Clock. 
  • XADC conversion requires 26 clocks
    • The DRP clock frequency must be selected carefully to achieve a rate of 1Msamples/sec.
    • Also, ensure that the FCLK from the SoC's PS side can generate the required frequency (see examples in link). 
Understanding Settling Time
  •  The XADC can be seen as a switch capacitor input, therefore, it is necessary to ensure that the voltage across the XADC's input capacitor has settled to its final value before sampling voltage. 
  • The XADC has a 12-bit resolution so, the voltage across the capacitor must settle to within 1/2 LSB of a 12-bit value.
    • 1/2 LSB I think is the max step error that can be tolerated (edaboard.com).
    • least significant bit within +1/2 and -1/2 of the value (wikipedia).   
  • The XADC assigns 75% of the sampling perod for settling time as the acquisition and conversion are happening.
    • For example, 1Msamples/sec sample rate allows 750 nsec for the input capacitor to settle to its final value.

Calculating Settling Time

 SettlingTime = 9.01 * 2R * C
  
Where: 2R = Resistance (due to differential input); 
9.01 = the number of time constants required to settle to the required accuracy 
C = capacitance

 For the XADC, Internal R = 10 kOhm; C = 3pF


Note as the conversion rate is slowed, the settling time is increased. Also, by putting more channels in the sequence, the time between updates is increased however, the resulting per-channel update rate should still be fast enough.






http://zedboard.org/content/microzed-chronicles

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