Problem Running on FPGA

If you encounter a problem where you are unable to run a program on the FPGA board after it has been programmed, here are some things to try:

1) Instead of right clicking on the folder --> Run As --> Launch on Hardware GDB, try running it using the green play button at the top of SDK

2) If you are still unable to run, try relaunching SDK from Vivado and run it again.

Comments

Post a Comment

Popular posts from this blog

Adam Taylor MicroZed Chronicles: Interrupt Latency

Image
Continuing with Adam Taylor's tutorials in his MicroZed Chronicles on the XADC. This post relates to issue 105, which can be found using the link at the bottom of the page. What I learned from Adam's Tutorial: Interrupt Latency: The time between the interrupt being raised and the interrupt being serviced. Once a signal is in the XADC and the Zynq SoC, it is necessary to ensure that the application has been designed properly to meet the requirements and perform in the way intended. Interrupt latency plays a major role in performance.  Some issues that can impact interrupt latency are: The presence of an operating system The complexity of the ISR (Interrupt Service Routine) If interrupt latency is not considered, the application could fail depending upon the latency period, latency consistency and the time taken for the ISR. If latency is too great or ISR execution is too long, events can be missed. When this happens, it results in an unreliable system with sp...
Read more

Using the XADC Header to Read Voltages

Image
First and foremost the most important thing to specify for the XADC Header are the pinouts. Looking at the Zedboard head on, the xadc header pins correspond to the picture directly above. Vn being the pin at the top right of the xadc header. For this project we will be reading the difference between two voltage inputs within the terminal. The pins are deferentially paired and you will get the difference between Vaux8p and Vaux8n. We will be connecting Vaux8P and Vaux8N to voltages and then Vref and all three AGNDs to ground. **Note: After further investigation we found that you should only need both Vaux pins and the three AGND and it should work the same.  We created two voltage dividers to provide the input voltages for the Vaux8 pins. We ended up inputting about 0.75 Volts into Vaux8P and about 0.50 Volts into Vaux8N. Below is a picture of the outputs from within the terminal: In the terminal, Vaux8 should be reading the difference between the inputs fo...
Read more

ADC/DAC and Digital Audio Processing

https://embeddedcentric.com/adc-dac-and-digital-audio-processing/ LAB 8 ***Helpful Note: The tutorial doesn't specify this, but you will need minicom open when running the program. Also if a warning appears after you have created the HDL wrapper you should be okay to continue anyway. Summary: In this lab, we use the ADAU1761 audio codec chip (coder-decoder) mounted on the Zed board, to output different pitches using the switches. Inside the codec are two ADCs, Right Channel and Left Channel, that we used to sample audio. The NCO generates samples of the sine waves at the designated frequencies and these samples are superpositioned and sent to the DACs through the I2S bus, so that they can be played on the speaker. ADAU1761 is and audio codec chip located on the Zedboard used for audio processing. Used for acoustic purposes (playing, recording, processing). The sample frequency is generated by the PLL logic which is driven by a master clock supplied by an external s...
Read more