Adam Taylor MicroZed Chronicles: The XADC's External Mux

Continuing with Adam Taylor's tutorials in his MicroZed Chronicles on the XADC. This post relates to issue 182, which can be found using the link at the bottom of the page.

What I learned from Adam's Tutorial:
The XADC has external analog multiplexer capability. It can interface with up to 17 analog inputs. One being the the Vp/Vn pair of inputs and the other 16 auxiliary differential pairs that share pins with the logic I/O. So, we can sample up to 17 different analog signals along with the on-chip supply voltages and temperatures.

An External Multiplexer provides the ability to sample up to 16 analog inputs. We only need 4 I/O lines for the multiplexer address because the Vp/Vn pair are dedicated and are outside of the multiplexer address.

Integrated Logic Analyzers (ILAs) monitor the internal signals of the design.

 Vivado

Create New Block Design

Add Zynq Processing System
Add xadc wizard
Add 2 ILAs

Double Click ila_1
  • Select Native > Change the number of probes to 4 > Change the Sample Data Depth to 16384
  • Under the Probe Ports Tab change Probe0 width to 5 > Ok
Double Click ila_0
  • Change Data Depth to 16384 
  • Under Monitor Interface0 
    • Change AXI Protocol to AXI4S
    • AXIST DATA Width to Manual 16, Manual 5, Manual 0, Manual 
    • OK
XADC Wizard
  • Startup Channel Selection to Channel Sequencer
  • AXI4Stream Options
    • Check Enable AXI4 Stream 
    • FIFO Depth 32
  • Alarms
    • Uncheck All Alarms
  • ADC Setup
    • Check External Multiplexer
    • Change the Channel for MUX = VP VN
    • OK 
Processing System
  • MIO Configuration
    • Memory Interfaces
      • Check Quad SPI Flash 
  • I/O Peripherals
    • Check Enet0 > MGIO
      • Check MDIO > MIO
    • Check USB0
    • Check USD0
    • Check SDO
      • Check CD > MIO > 47
      • Check WP > MIO > 46
    • Check UART1 
    • GPIO
      • Check GPIO > MIO
  • Clock Configuration
    • Expand IO Peripheral Clocks
      • SDIO > Requested Frequency > 50
    • Expand PL Fabric Clocks
      • Check FCLK_CLK0 > Requested Frequency > 100 
  • DDR Configuration
    • DDR Controller Configuration > Check Internal Vref
  • Interrupts
    • Check Fabric Interrupts > Expand
    • Expand PL-PS > Check Care0_nIRQ 
  • OK 
Run Connection Automation

Further Connections:
  1. ila_1
  • Connect Probe 0 to (XADC) channel_out
  • Connect Probe 1 to (XADC) eoc_out
  • Connect Probe 2 to (XADC) eos_out
  • Connect Probe 3 to (XADC) busy_out 
   2. ila_0
  • connect SLOT_0 to (XADC) M_AXIS  
   3. XADC Wizard
  • Vp_Vn > Make External  
   4. Processing System
  • DDR > Make External
  • Fixed_io > Make External   
Run Connection Automation

  5. NOW YOU MUST MAKE A CONSTRAINTS FILE

**Note: The VP and VN are dedicated inputs, therefore they do not need to be declared in the .xdc

  We used the constraints kindly provided to us by Adam Taylor:


**If you don't know how to make a constraints file (.xdc) in Vivado refer to Emily's Blog Post "Making a Constraints File."

Once the Constraints file is complete we are now ready to export to SDK:

Save > Validate > Create HDL Wrapper > Generate Bitstream > Export Hardware > Launch SDK


SDK

Now you want to import Adam Taylor's SDK files from Ex_Mux.xpr.zip

**If you don't know how to import an SDK file refer to Sam's post "Opening Projects in SDK."


To continue on, refer to blog post "External Mux Continued."




Thanks to Adam Taylor for providing us with the resources and help for this project!

https://forums.xilinx.com/t5/Xcell-Daily-Blog/Adam-Taylor-s-MicroZed-Chronicles-Part-182-The-XADC-s-External/ba-p/758373

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