FPGASiena2017

 A LOW-PASS filter is a filter that sets a frequency, typically referred to as the cutoff frequency or the passband, and keeps all signals lower than the set frequency, and reduces the signals that are higher than the set frequency, which is typically referred to as the stopband. The process of removing unwanted frequencies  allows for a more accurate data set and easier recognition of trends. This process is commonly used to clean up signals, remove noise, perform data averaging, and recognize patterns.   A HIGH-PASS or bass-cut filter, is a filter that sets a "cut-off" frequency and keeps all signals higher than the cut-off, the passband, and reduces the signals lower than the cut-off, the stopband. This process is commonly used to "clean up" low frequency noise, remove unnecessary sounds and audio signals, redirect higher frequency signals, and highlights high frequency trends by removing low frequency trends. Sources: https://www.mathworks.com/disc...

Simple Screen Recorder is used for capturing your computer screen to make a video. To download Simple Screen Recorder, open a Terminal and type: $ sudo add-apt-repository ppa:maarten-baert/simplescreenrecorder  $ sudo apt-get update $ sudo apt-get install simplescreenrecorder Use the following link to help specify the settings: https://www.tecmint.com/screencasting-with-simple-screen-recorder-in-linux/ When using a USB microphone you must change the source for it to work. Navigate to the Audio Input section within the settings and choose the USB option next to source. If you don't see the USB, try the refresh button. If using the USB mini microphone the source should say something like, USB PnP Sound Device Analog Mono.

The pin-outs for the Analog Discovery Legacy correspond with the below diagram.

To make a constraints file in Vivado following these steps: 1. Open the block design 2. Under the Sources tab, open the constraints folder 3. Right click on the constrs_1 folder and click on Add Sources 4. You can either add a constraint file from your computer or create your own We have the complete set of Zedboard constraints located on the SienaFPGA2017 Github page.

First and foremost the most important thing to specify for the XADC Header are the pinouts. Looking at the Zedboard head on, the xadc header pins correspond to the picture directly above. Vn being the pin at the top right of the xadc header. For this project we will be reading the difference between two voltage inputs within the terminal. The pins are deferentially paired and you will get the difference between Vaux8p and Vaux8n. We will be connecting Vaux8P and Vaux8N to voltages and then Vref and all three AGNDs to ground. **Note: After further investigation we found that you should only need both Vaux pins and the three AGND and it should work the same.  We created two voltage dividers to provide the input voltages for the Vaux8 pins. We ended up inputting about 0.75 Volts into Vaux8P and about 0.50 Volts into Vaux8N. Below is a picture of the outputs from within the terminal: In the terminal, Vaux8 should be reading the difference between the inputs fo...

To connect the pins of the XADC header to anything, such as a voltage divider, we use the following image:     The image of the pins are actually opposite than what is posted in the Zedboard User Guide. If you are looking at the Zedboard straight on, it is the upside down image of the one that is in the User Guide. Attached above are the correct images of the way the pins should be connected.

We created a Github to store our projects. SienaFPGA2017. The following link provides a helpful tutorial for using Github directly: https://guides.github.com/activities/hello-world/ *********************************************************************************** The following link provides a helpful tutorial for using the terminal to upload a project to Github: https://www.howtoforge.com/tutorial/install-git-and-github-on-ubuntu-14.04/ Some of the basics: gedit ---- Creates a file where you can copy and paste in something like a code or just write a brief description. git add ---- Adds the created files into the index git commit -m "some_message" ---- Commits changes made in the index git remote add origin "copy https from newly made github repository" ---- connects the files to the github web address git push origin master ---- Moves the files to githuhb

Often times a version of a program can have random glitches that prevent us from executing simple tasks that wouldn't normally be an issue. We encountered this problem when trying to launch SDK 2016.2 in the newer version of Ubuntu. To avoid this glitch: - Navigate to /opt/Xilinx/SDK/2016.2 in the terminal - ls - You should see a file, settings.sh - Type command ./settings64.sh - Type command export SWT_GTK3=0 - Now type /opt/Xilinx/SDK/2016.2/bin/xsdk SDK SHOULD LAUNCH!! https://www.xilinx.com/support/answers/68490.html

After exporting the design to SDK and importing Adam Taylor's Software Files, we can now import a signal (voltage). First we must modify Adam's .h and .c files to read the VP and VN. In helloworld.c change:  XSysMon_SetSeqChEnables( SysMonInstPtr,                                               XSM_SEQ_CH_AUX00|                                               XSM_SEQ_CH_AUX08); to... XSysMon_SetSeqChEnables( SysMonInstPtr,                XSM_SEQ_CH_VPVN ); AND ...

Continuing with Adam Taylor's tutorials in his MicroZed Chronicles on the XADC. This post relates to issue 182 , which can be found using the link at the bottom of the page. What I learned from Adam's Tutorial: The XADC has external analog multiplexer capability. It can interface with up to 17 analog inputs. One being the the Vp/Vn pair of inputs and the other 16 auxiliary differential pairs that share pins with the logic I/O. So, we can sample up to 17 different analog signals along with the on-chip supply voltages and temperatures. An External Multiplexer provides the ability to sample up to 16 analog inputs. We only need 4 I/O lines for the multiplexer address because the Vp/Vn pair are dedicated and are outside of the multiplexer address. Integrated Logic Analyzers (ILAs) monitor the internal signals of the design. Vivado Create New Block Design Add Zynq Processing System Add xadc wizard Add 2 ILAs Double Click ila_1 Select Native > Change the number...

To open a project in SDK you must import it: Open SDK > Choose workspace File > Import > General > Existing Projects into Workspace > Next Browse for the root directory that contains your project Select copy projects into Workspace > Finish Click on the Workspace icon to open your project if it doesn't open automatically Helpful Link for importing an existing Software Project:  https://www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/SDK_Doc/tasks/sdk_t_import_exist_proj.htm

Continuing with Adam Taylor's tutorials in his MicroZed Chronicles on the XADC. This post relates to issue 107 , which can be found using the link at the bottom of the page. What I learned from Adam's Tutorial: This tutorial is a continuation of issue 105 and 106. We can now define the hardware we want to pull into SDSoC from Vivado. Knowing and designing for latency has ensured that we will never miss an XADC sample. Recall from Issue 104 that we can sample at 961.54 ksamples/sec (ksps) using a 100MHz AXI clock frequency. So, a new sample and corresponding interrupt will occur every 1.04 microseconds. Vivado Modifying our Vivado design from the interrupt latency posts. We will remove axi_timer_0 and replace it with the xadc_wiz. Be sure to save this as a new project so you don't lose the old design.  1. Delete axi_timer_0 2. Add xadc_wiz > Run Connection Automation 3. Right Click on Vp_Vn and make external 4. Connect (xadc_wiz) ip2intc_irpt to (PS) core0...

On Mac OSX 1. Go to digilentinc.com 2. Find Waveforms 2015 > Download Here The top tab should read: Diligent Documentation > Reference > Software > Waveforms > Waveforms 2015 3. Go to the latest downloads and select the download for Mac OSX 4. Download and then double click to open 5. Drag Waveforms into Applications 6. To support analog discovery install the followng driver: Double click DigilentFtdiDriver.pkg 7. We need to change the security settings if it can't download. 8. Go to the apple in the top left hand corner of your screen > System Preferences > Security and Privacy > Open Anyway > Continue > Continue > Continue > Agree to terms > Install > Enter password for the computer > Install software 9. Open Applications folder > double click on Waveforms to open Again, we must change the security and privacy settings. 10. Security Systems > open anyway > open. On Linux (Ubuntu) 1. Go to digilentinc.com 2. Fi...

Continuing with Adam Taylor's tutorials in his MicroZed Chronicles on the XADC. This post relates to issue 106, which can be found using the link at the bottom of the page. What I learned from Adam's Tutorial: This tutorial is a continuation of issue 105. Here, the interrupt latency we will be measuring is the time required to start executing the ISR. We left off in Vivado having just created the Bitstream. Now we are ready to move into SDK. Export Hardware > Check Include Bitstream > Launch SDK Once in SDK: File > New > Board Support Package > Finish File > New > Application Project > Hello World > Finish Copy and paste in the .C file from Adam Taylor's github (https://github.com/ATaylorCEngFIET/MicroZed-Chronicles) and replace it with helloworld.c and SAVE IT. Next launch minicom > Program FPGA > Run You should see something similar to this within minicom:   This is reading the value on the AXI Timer as soon as the ...

Continuing with Adam Taylor's tutorials in his MicroZed Chronicles on the XADC. This post relates to issue 105, which can be found using the link at the bottom of the page. What I learned from Adam's Tutorial: Interrupt Latency: The time between the interrupt being raised and the interrupt being serviced. Once a signal is in the XADC and the Zynq SoC, it is necessary to ensure that the application has been designed properly to meet the requirements and perform in the way intended. Interrupt latency plays a major role in performance.  Some issues that can impact interrupt latency are: The presence of an operating system The complexity of the ISR (Interrupt Service Routine) If interrupt latency is not considered, the application could fail depending upon the latency period, latency consistency and the time taken for the ISR. If latency is too great or ISR execution is too long, events can be missed. When this happens, it results in an unreliable system with sp...

Continuing with Adam Taylor's tutorials in his MicroZed Chronicles on the XADC. This post relates to issue 104, which can be found using the link at the bottom of the page. What I learned from Adam's Tutorial: An XADC is used to read in an analog signal and process the information. To interface with the XADC an AXI interface is needed Interface Options Include:  Connecting with an AXI4-Lite Interface Adding an AXI streaming interface to add further signal processing (like the FIR Filter) The first choice that needs to be made is the selection of the input pins The XADC has two dedicated differential input pins, Vp and Vn, which can be used to sample analog signals. There are also 16 auxiliary inputs that can be used. These have a lower FRBW (Full Resolution Bandwidth) of 250 kHz whereas the dedicated inputs have an FRBW of 500 kHz . If using signals near the max Nyquist frequency, use the dedicated  inputs.  If there are more than one signal ...

Continuing with Adam Taylor's tutorials in his MicroZed Chronicles on the XADC. This post relates to issue 43, which can be found using the link at the bottom of the page. What I learned from Adam's Tutorial: The Zynq SoC has the ability to monitor its own supply voltages and temperature. We can use this ability to verify the initial supply voltages and operating temperature. We can also check to ensure that the parameters remain within the specified ranges throughout operation.  This can help us to determine if the Zynq SoC's environment has any problems that could possibly result in a failure over time. An example could be a drifting power supply. The SoC has a number of maskable interrupts that can interrupt the 2 on-chip ARM processors if an alarm parameter exceeds its range. A maskable interrupt can be disabled by the programmer, so if an interrupt happens, the CPU can ignore it and not have to respond. Above definition from: https://www.quora....

Adam Taylor has multiple tutorials in his MicroZed Chronicles on the XADC. This post relates to issue 7 and 8. These can be found using the link at the bottom of the page. What I learned from Adam's Tutorials: The Zynq SoC's XADC block contains two 12-bit ADC inputs with additional input channels connected to on-chip voltages and temp sensors.   The XADC is capable of unipolar (only + or only -) or bipolar (both + and - range) measurements. Each analog input is differential. The 17 differential inputs are split between one dedicated analog input pair (VP/VN) and 16 auxiliary inputs that can be configured as either analog or digital I/O pins (VAuxP/VAuxN). The effective input signal band width depends on which input is being utilized VP/VN = 500kHz Axiliary = < 251kHz To add the XADC to the Block Diagram Add the Zynq Processing System and the XADC Wizard then run the block automation and the connection automation. It should look similar to the picture b...

https://embeddedcentric.com/adc-dac-and-digital-audio-processing/ LAB 8 ***Helpful Note: The tutorial doesn't specify this, but you will need minicom open when running the program. Also if a warning appears after you have created the HDL wrapper you should be okay to continue anyway. Summary: In this lab, we use the ADAU1761 audio codec chip (coder-decoder) mounted on the Zed board, to output different pitches using the switches. Inside the codec are two ADCs, Right Channel and Left Channel, that we used to sample audio. The NCO generates samples of the sine waves at the designated frequencies and these samples are superpositioned and sent to the DACs through the I2S bus, so that they can be played on the speaker. ADAU1761 is and audio codec chip located on the Zedboard used for audio processing. Used for acoustic purposes (playing, recording, processing). The sample frequency is generated by the PLL logic which is driven by a master clock supplied by an external s...

If you encounter a problem where you are unable to run a program on the FPGA board after it has been programmed, here are some things to try: 1) Instead of right clicking on the folder --> Run As --> Launch on Hardware GDB, try running it using the green play button at the top of SDK 2) If you are still unable to run, try relaunching SDK from Vivado and run it again.